#494 HyGCN: A GCN Accelerator with Hybrid Architecture

Inspired by the broad use of graph data and powerful learning capability of neural networks, graph convolutional neural networks (GCNs) are proposed to analyze graph datasets using neural networks. The convolutional layers occupy the major execution time of GCNs through two primary execution phases: \emph{Aggregation} and \emph{Combination}. The former behaves as graph processing while the latter acts more like the neural networks. In order to identify the bottleneck when performing GCNs, we conduct quantitative characterizations that evidence the inefficiency in the conventional architectures. This is caused by the distinct, even opposed, memory access and computation patterns of the two phases, as well as the serialized processing of them. To address these issues, we propose the concept of GCN accelerator and implement it using a hybrid architecture. First, we build Edge- and MVM (matrix vector multiplication)-centric programming models for the dynamic & irregular \emph{Aggregation} phase and the static & intensive \emph{Combination} phases, respectively, to achieve the hardware transparency for programmers. Then, we design \emph{HyGCN} with two efficient processing engines to respectively accelerate the two phases. In \emph{Aggregation Engine}, besides the edge parallelism achieved by SIMD cores, we introduce the interval-shard graph partition to increase data reuse and the window sliding-shrinking method to decrease redundant accesses. In \emph{Combination Engine}, we build multigranular systolic arrays to perform MVMs that can flexibly be used in an independent way for lower latency or in a joint way for lower energy. At last, we further optimize the overall system via orchestrating the inter-engine pipeline and off-chip memory access coordination. Through extensive evaluation experiments, our work achieves significant improvements compared with the state-of-the-art software framework running on Intel Xeon CPU. We also analyze the optimization techniques and design space to give more insights for future researches on GCN hardwares.